REFLEX CES, with 17+ years of experience designing with FPGAs (Altera/now Intel PSG and Xilinx) can assist our customers with an interface mapping verification process using Vendor tools (Quartus and Vivado).
The goal is to study the balance of critical resources such as Memory (DDR2/3/4, QDR2/2+/4, Flash…), high-speed transceivers (up to 28Gbps for current devices), as well as general purpose IOs, clocking and power trees. Following this full analysis, a report is delivered with our conclusions and recommendations.
ReFLEX CES, using our experience in complex systems, can also guide our customers during the architectural stage and can help choose the right devices to address the project requirements.
FPGA design :
VHDL and Veriloglanguages
Stratix families, Arria families, Cyclone families, Max families from Intel PSG (formerly Altera)
Virtex families, Kintex, Artix families from Xilinx
Implementation of development tools: Quartus Prime, Vivado, SignalTap, ISE, ChipScope/ILA, Transceiver Toolkit, IBERT, ModelSim
IP designs and implementation: PCIe, 10/40/100GbE, Memory controllers (DDR2/3/4, QDR2/2+/4…), Serial Lite, Aurora, Profinet, Gigabit Vision, …
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