The High Performance Computing (HPC) OpenCL™ BSP implements Global Memory and PCIe interface support for OpenCL™-coded kernels targeting Arria 10 FPGA Accelerator Boards from REFLEX CES.
DDR-based Global memory
PCIe Gen 3
Heterogeneous memory support (DDR4/QDR2+)
Latest Quartus release support (16.1.2 / 17.0)
10G Low Latency MAC OpenCL™ BSP
This BSP offers 4 x 10GbE Low Latency MAC IPs as well as the complete HPC BSP features (PCIe + Global Memory). OpenCL™ developers can directly connect their acceleration kernels to the MAC through IO Channels.
Standard 10G Low Latency MAC IP from Intel/Altera
180ns round trip latency performance
4 independent 10Gb MAC links mapped to a QSFP connector
Timestamp counter (10ns precision)
Functional OpenCL™ examples
Host-In-HPS OpenCL™ BSP
This BSP implements the host processor inside the SoC FPGA (HPS ARM processor). This concept allows an autonomous embedded system to consider OpenCL™ flow even if no x86 processor is available.