Hardware Acceleration on FPGA with OpenCL™

REFLEX CES OpenCL™ Board Support Package (BSP) enables developers to code parallel C-code accelerator kernels and target FPGAs.

OpenCL and the OpenCL logo are trademarks of Apple Inc. used by permission by Khronos.


The High Performance Computing (HPC) OpenCL™ BSP implements Global Memory and PCIe interface support for OpenCL™-coded kernels targeting Arria 10 FPGA Accelerator Boards from REFLEX CES.

  • DDR-based Global memory
  • PCIe Gen 3
  • Heterogeneous memory support (DDR4/QDR2+)
  • Latest Quartus release support (16.1.2 / 17.0)
  • Partial Reconfiguration
Diagram HPC OpenCL™ BSP

10G Low Latency MAC OpenCL™ BSP

This BSP offers 4 x 10GbE Low Latency MAC IPs as well as the complete HPC BSP features (PCIe + Global Memory). OpenCL™ developers can directly connect their acceleration kernels to the MAC through IO Channels.

  • Standard 10G Low Latency MAC IP from Intel/Altera
  • 180ns round trip latency performance
  • 4 independent 10Gb MAC links mapped to a QSFP connector
  • Timestamp counter (10ns precision)
  • Functional OpenCL™ examples
Diagram 10G Low Latency MAC OpenCL™ BSP

Host-In-HPS OpenCL™ BSP

This BSP implements the host processor inside the SoC FPGA (HPS ARM processor). This concept allows an autonomous embedded system to consider OpenCL™ flow even if no x86 processor is available.

  • Embedded host processor inside the SoC
  • Embedded Linux (Angstrom)
  • Independent DDR banks (HPS/FPGA)
  • Bootloader / File system in Flash memory
Diagram Host-In-HPS OpenCL™ BSP

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