Alaric DevKit

Product overview

The Arria® 10 SoC FMC Instant-Development Kit provides to developers the best Out-Of-The box experience combining the Best-In Class compact hardware platform and the most efficient intuitive software environment.

Its unique install and GUI interface allows an immediate start, and its reference designs enable fast turn-around designs shortening and securing the developments.

The target markets are as wide as Video capture and processing, Industrial, Test & Measurement and Medical.

Benefits & features

  • Designed for high performance serial transceiver applications using series 10 SoC Intel FPGAs
  • Intel Arria® 10 SoC 660 KLEs in F34 package compliant 660 KLEs
  • Hardware, software design tools, IP, and pre-verified reference designs
  • PCIe device with 4 lanes at 8 Gb/s link rate (Gen3) and PCIe root with 4 lanes at 8 Gb/s link rate (Gen3)
  • Advanced memory interface with DDR3 on board Memory up to 4GB
  • Develop networking applications with 10/100/1000 Mbps Ethernet (GMII, RGMII and SGMII​)
  • Implement Video display applications with Display output port (up to 5.4Gbit/s)
  • The board respects the VITA57.1 standard, you can plug FPGA Mezzanine Card (FMC) on the front end
  • The FMC interface provides High Pin Count (HPC) fully populated, compliant +1.8V only ( +vadj):
    • 160 LVCMOS (1.8V) usable as 80 LVDS (1.8V, 2.5V)
    • 4 dedicated LDVS clocks that respect the VITA57.1 pinout assignment usable as LVDS signals or 8 LVCMOS
    • 10 XCVR (up to: 14.2 Gb/s)





Bloc diagram of the Alaric Devkit



Tech specs

Featured Device

  • Board based on Intel® Arria® 10 SoC 660KLEs, speed grade -2 (10AS066H3F34I2SG)
  • PCIe end point edge connector for Gen3 x4 (32Gb/s)
  • PCIe root Complex edge connector for Gen3 x4 (32Gb/s) (not tested with PCIe Root IP)
  • FMC High Pin Count fully compliant:
    • 168 LVCMOS (1.8V) or 84 LVDS (1.8V,2.5V)
    • 10 XCVR (Typical 10Gb/s)
  •  One serial over USB High speed link (through USB Hub)
  • 2 x RJ45 copper connector 10/100/1000Base-T Ethernet connected to the FPGA core fabric part
  • 1 x RJ45 copper connector 10/100/1000Base-T Ethernet connected to the HPS part of the FPGA
  • On board DDR3 for HPS (2GB) speed up to 2133 MT/s
  • On board DDR3 for FPGA (2GB) speed up to 2133 MT/s
  • DisplayPort Rev1.2 (up to 5.4Gbit/s)
  • One microSD 8 GB SDHC Class 10 (already insert into the support connector) with factory image boot
  • Mini USB connector B-type to enable the USB2.0 PHY OTG high speed, ULPI interface connected to the HPS of the FPGA
  • MAX 10 Power supplies monitoring with its ADCs solution
  • Innovative clock tree (Silicon Labs)
  • +12V on a JACK/Edge PCIe connector / ATX connector
  • Active Heat sink
  • PCIe Bracket, LED
  • SATA connector to FPGA 1 x XCVR
  • MCX connector for PPS interface
  • Mictor connector for HPS debug trace

Board Programming

  • JTAG : On-board USB-Blaster II MAX V (reachable by USB Hub)
  • Fast passive parallel (FPP) configuration via MAX®10 device and flash memory
  • AS configuration supported with NOR FLASH
  • Boot selection for HPS throught user dipswitch

Clock circuitry

  • 3 x SMA connectors (1 main input clock + 1 diff. output programmable clock)
  • 9 x FPGA XCVR programmable inputs Clocks (up to 800 MHz to reach different communication protocol)

Board size

  • Length : 240 mm (9.45 inches)
  • Height : 111.15 mm (4.38 inches) / Standard Height PCIe
  • Standard Thickness PCIe

Power & Environment

  • Power : 75W max/ 40W typical
  • Environmental : 0°C/ +60°C


DevKit Alaric

  • Alaric Arria® 10 SoC FMC PCIe board with active heatsink
  • Power adapter (US, UK, EU, JP) and Micro USB2.0 cable
  • One microSD 8 GB SDHC Class 10
  • PDF Documentation (Starter Guide, Hardware Reference Manual, Board Outline)
  • FMC Interface Control Excel sheet
  • HDL Test Designs (Quartus projects) & Software Board Support Package for Hard Processing System Interface (HPS)
  • Under request at :
    • Mechanical files (DWF/STEP models and 2D drawing)


Ordering informations

  • RXCA10S066PF34-IDK00A



ECCN Number : 4A994i

CECC (commodity Export Classification Certificate) : Download certificate


What is the Alaric Instant Devkit ?

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This Development Kit respects the PCIe form factor with a standard height size. All the mechanical constraint rules are respected to allow the insertion of the Alaric board into a PCIe rack through its PCIe edge, by 4 connector and + 12 Volts PCIe connector supply.

This board offers a FMC front end interface to plug mezzanine card and access to 80 LVDS signals directly connected to the FPGA SX, usable as 160 LVCMOS single ended signal. On this interface you also have 10 Transceivers links up to 10 Gbps for each lane.

You can also connect your Alaric board to the network with a 10/100/1000 BaseT Ethernet interface with standard RJ45 connectors; two are directly connected through RGMMI PHY component to the HPS and one is connected on the fabric logic of the FPGA.

You can manage 8 internal clocks up to 800 MHz onboard with innovative programmable PLL drive by I²C bus connected to the CPLD MAX10 and the FPGA Arria® 10 SX.

This board is designed for prototyping PCIe host port by using the PCIe root Complex edge connector for Gen3 x4 (32Gb/s)

Finally, the Alaric board has a high end digital core based on Arria® 10 SX. It is connected to a 4GigaByte DDR3 component and offers two independent banks, one connected to the HPS of the FPGA.

->For more details about the Alaric PCIe FMC board and to get documentation, please email or go on

How to program my MAX 10 and Arria® 10 on my Alaric board ?

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You must use Quartus programmer tools through USB blaster on board to reprogram the Development Kit, please check the latest Quartus version with your Intel FAE

Scenario 1:  You can program the FPGA Arria® 10 and (or) the MAX10 through USB blaster in JTAG mode.

Scenario 2: You can program the Arria® 10 with an image that is contained in Flash, in FPP 32 configuration mode.

Scenario 3:  At power-up, Arria® 10 automatically loads via a quad serial interface with its dedicated NOR FLASH, in AS configuration mode.

Scenario 4: “Configuration via Protocol”: One minimal configuration is contained in the NOR Flash. This binary is loaded in the FPGA allowing to improve the PCIe access and permits to the software to load external image in the Arria® 10 (Configuration via Protocol (CvP))

Power supply monitoring:  the MAX 10 integrates Analog-to-digital converters (ADCs) to control power monitor system with the Intel modular ADC IP core implemented in it.

Serial communication: the MAX 10 integrates a serial logic bloc to enable an external communication (UART), the operator can take control through the USB front interface.

Programming system: You can program the Arria® 10 with an image that is contained in Flash. The MAX 10 integrates Parallel Flash Loader IP Core that allows to enable a FPP 32 configuration mode.

Configuration system: Partial reconfiguration IP Core has been instantiated. One minimal configuration can be uploaded into the Flash. This binary can be loaded in the FPGA during normal activity without any reboot and enables or redefines functions into the FPGA.

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