Tech spec
Form Factor
- Low Profile PCIe
- Half height, half length
- Single slot width
- 6.59 x 2.71 inches
FPGA processing
- EP5SGXEA7K2F40C2 28-nm FPGA, compatible with EP5SGXEA7622000 Logic Elements
- 938880 registers
- 7145 KB internal memory
- 512 18x18 multipliers
- 256 27x27 DSP blocks
DDR3 SDRAM memory
- 2 banks, 72-bit
- 2 x 4GB @ 1600 MT/s
QDR2+ SRAM
- 2 banks, 18-bit, SIO
- 2 x 18MB @ 800MT/s
Non-volatile memory
- 512MB NOR Flash (32-bit)
- 2x1KB I2C EEPROM
Clock sources (MHz)
- 25, 50, 100, 125, 200, 644.53125
Board to Board interface
- 4 GTH transceiver pairs
- I2C bus plus 3 LVCMOS I/Os
Host interface
- Physical: PCI Express 3.0 x 8 (8-lane)
- Logical: x1, x2, x4, x8 at Gen3, Gen2, Gen1 speed.
Backplate interface
Two SFP+ interfaces which use FPGA transceivers allowing:
Transceivers reference clock are fed by 644,53125 MHz LVDS oscillator
Each SFP+ interface has its own dual Tricolor LED on the front bracket for Ethernet link display + others
Time stamping interface
- IEEE-1588 PTP over RJ45 through National DP83640
General purpose I/Os
- 2x3 LED on front panel bracket
- 8 x user LEDs
- 4 x FPGA configuration LEDs
- 1 x reset button
- 1 x FPGA configuration reload button
- 1 x FPGA image boot selector
- 3 x user switches
Quality and compliance
- ISO9001 production facility
- RoHS, REACH
- IEC 60950-1 / CB scheme
FPGA configuration
- JTAG (USB cable)
- CPLD & Flash Engine
- Support for 2 bitstreams
- Bitstream updates via Host software through PCIe
- Golden bitstream recovery
- FPGA partial configuration via host (PRC)
- Auto recovery from bad user bitstream
Electrical and power
- Power derived from PCIe slot 3.3V and 12V
- A7: 30W Typical / max 50W.
Low Latency
- Measured 200ns 10GbE wire to FPGA fabric through optional 10G Ethernet MAC and 10G TCP hardware stack
Cooling
- Active cooling with low profile heatsink + fan
Environmental
- Cooling: Air convection
- Operating temperature: 0°C to 70°C
- Storage temperature: -20°C to 80°C
- Relative humidity: 45 to 95% (non-condensing)
