Arria 10 SoC FMC PCIe board

Product overview

The Arria 10 SX FMC PCIe board provides to customers an on-the-shelves Best-In Class hardware solution, which is from one end extremely compact and optimized, and from the other end very opened to multiple applications by using the FMC High-Pin-Count interface and scalable DDR3 memory connected to the HPS and FPS part for the FPGA.

Benefits & features

Designing for high performance serial transceiver applications using series 10 SoC ALTERA FPGAs
ALTERA Arria 10 SoC 660 KLEs in F34 package compliant 660 KLEs

Hardware, software design tools, IP, and pre-verified reference designs.
PCIe device with 4 lanes at 8 Gb/s link rate (Gen3) and PCIe root with 4 lanes at 8 Gb/s link rate (Gen3)
Advanced memory interface with DDR3 on board Memory up to 4GB
Develop networking applications with 10/100/1000 Mbps Ethernet (GMII, RGMII and SGMII​)
Implement Video display applications with Display output port (up to 5.4Gbit/s)

The board respect the VITA57.1 standard, you can plug FPGA Mezzanine Card (FMC) on the front end
The FMC interface provides High Pin Count (HPC) fully populated, compliant +1.8V only ( +vadj)

  • 160 LVCMOS (1.8V) usable as 80 LVDS (1.8V, 2.5V)
  • 4 dedicated LDVS clocks that respect the VITA57.1 pinout assignment usable as LVDS signals or 8 LVCMOS
  • 10 XCVR (up to: 14.2 Gb/s)*

* Production Device with transceiver speed grade 3 can reach 14.2 Gb/s chip to chip links, The VITA 57.1 standard allows interfaces up to 10 Gb/s

Diagrams

Tech spec

Featured Device

FPGA Arria 10 GX 10AS066H3F34I2SG (660K LEs in F34 package FBGA / production device) compliant 570/ 320/ 270 KLEs

Board & soft programming

  • On board JTAG configuration circuitry to enable configuration over on board USB blaster
  • JTAG header provided to program the MAXV and access to the ARRIA 10.
  • Fast passive parallel (FPP) configuration via MAX®10 device and flash memory
  • Active Serial (AS) configuration via 128MB (1024Mb) Quad serial SPI Nor Flash
  • AS configuration for CvP support
  • Hard Processor System (HPS) Configuration Device
  • Serial NOR FLASH -SPI 128 Mbits connected to the HPS of the FPGA
  • One microSD 8 Go SDHC Class 10 (already insert into the support connector) with factory image boot

Communication & Interfaces

  • PCIe edge connector for Gen3 x4 (32Gb/s)
  • 2 x RJ45 copper connector 10/100/1000Base-T Ethernet (Through RGMII PHY) connected to the Fabric logic of the FPGA.
  • 1 x RJ45 copper connector 10/100/1000Base-T Ethernet (Through RGMII PHY) connected to the HPS of the FPGA.
  • One serial over USB High speed link (through USB Hub)
  • Mini USB connector B-type to enable the USB2.0 PHY OTG high speed, ULPI interface connected to the HPS of the FPGA.
  • FMC High Pin Count (HPC) compliant 1V8 interfacePCIe Root connector for Gen3 x4 (32Gb/s)
  • 160 LVCMOS (1.8V) usable as 80 LVDS (1.8V, 2.5V)
  • 4 dedicated LDVS clocks that respect the VITA57.1 pinout assignment usable as LVDS signals or 8 LVCMOS
  • 10 XCVR (up to: 14.2Gb/s)*

Memories

  • 4 x SDRAM DDR3 (a bandwidth of 8 bits per component for a total depth of 2GB) up to 2133 MT/s connected to the Fabric logic of the FPGA
  • 4 x SDRAM DDR3 (a bandwidth of 8 bits per component for a total depth of 2GB) up to 2133 MT/s connected to the HPS of the FPGA
  • Serial NOR FLASH -SPI 128 Mbits
  • 32Kb I2C EEPROM

Other resources

  • DisplayPort  Rev1.2 (up to 5.4Gbit/s)
  • MicroSD Card connector
  • MAX 10 Power supplies monitoring with its ADCs solution
  • +12V on a JACK/Edge PCIe connector
  • LCD Monitoring
  • DIP Switches
  • Diff Pair I/O (1 SMA pair)
  • On board UART over USB solution on Max 10 (µUSB connector).

Clock Circuitry

  • System clock 100 MHz (Max 10 / Arria 10)
  • 3 SMA connectors (1 main input clock + 1 output programmable clock)
  • SILICON LABS tree innovative clock generation SI5341, on board PLL solution with very low Jitter which programmable 9 output clocks 100Hz to 800MHz LVDS to FPGA clock system
  • Input 0: Differential clock from PLL_CLKOUT FPGA output
  • Input 1: Single ended clock from SMA connector
  • Input 2: Dedicated default input clock for the SI341 from on board 100 MHz oscillator.

Board Size

  • Length : 240 mm (9.45 inches)
  • Height :  111.15mm (4.38 inches) / Standard Height PCIe
  • Thickness : 1.57 mm (0.062 inches) / Standard Thickness PCIe

Power

  • 12V wall adapter or ATX / cables (US, UK, EU, JP)
  • Voltage and Current measurement capability of 2.5V, 1.5V, and 1.2V, 1.0V supplies (I²C path to FPGA)

* Production Device with transceiver speed grade 3 can reach 14.2 Gb/s chip to chip links, The VITA 57.1 standard allows interfaces up to 10 Gb/s

Deliverables

Board content

  • Standard FMC Full Height PCIe board
  • One microSD 8 Go SDHC Class 10
  • PCIe standard bracket
  • Active Heat sink
  • Board support package (BSP) (upon request)
  • OpenCL HPC BSP (upon request)
  • OpenCL BSP Networking 10G UDP (upon request)

Ordering informations

Arria 10 SX board (FPGA prod Device) // RXCA10S066PF34-FHP00A

OpenCL BSP HPC (Host-In-x86) // RXCA10S0000F34-BSP00B (upon request)

OpenCL BSP HPC (Host-In-HPS) // RXCA10S0000F34-BSP00D (upon request)

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