Alaric Arria® 10 SoC FMC PCIe DevKit

Product overview

The Arria® 10 SoC FMC Instant-Development Kit provides to developers the best Out-Of-The box experience combining the Best-In Class compact hardware platform and the most efficient intuitive software environment.

Its unique install and GUI interface allows an immediate start, and its reference designs enable fast turn-around designs shortening and securing the developments.

The target markets are as wide as Video capture and processing, Industrial, Test & Measurement and Medical.

Benefits & features

Designing for high performance serial transceiver applications using series 10 SoC
ALTERA FPGAs ALTERA Arria® 10 SoC 660 KLEs in F34 package compliant 660 KLEs

Hardware, software design tools, IP, and pre-verified reference designs.
PCIe device with 4 lanes at 8 Gb/s link rate (Gen3) and PCIe root with 4 lanes at 8 Gb/s link rate (Gen3)
Advanced memory interface with DDR3 on board Memory up to 4GB
Develop networking applications with 10/100/1000 Mbps Ethernet (GMII, RGMII and SGMII​)
Implement Video display applications with Display output port (up to 5.4Gbit/s)

The board respect the VITA57.1 standard, you can plug FPGA Mezzanine Card (FMC) on the front end
The FMC interface provides High Pin Count (HPC) fully populated, compliant +1.8V only ( +vadj):

  • 160 LVCMOS (1.8V) usable as 80 LVDS (1.8V, 2.5V)
  • 4 dedicated LDVS clocks that respect the VITA57.1 pinout assignment usable as LVDS signals or 8 LVCMOS
  • 10 XCVR (up to: 14.2 Gb/s)*

* Production Device with transceiver speed grade 3 can reach 14.2 Gb/s chip to chip links, The VITA 57.1 standard allows interfaces up to 10 Gb/s

 

 

Diagrams

Tech spec

Featured Device

  • FPGA Arria® 10 SX 10AS066H3F34I2SG (660K LEs in F34 package FBGA / production device)
  • ROHS compliant Arria® 10 FPGA PCIe FMC Instant-DevKit

Board & soft programming

  • On board JTAG configuration circuitry to enable configuration over on board USB blaster
  • JTAG header provided to program the MAXV and access to the Arria® 10.
  • Fast passive parallel (FPP) configuration via MAX®10 device and flash memory
  • Active Serial (AS) configuration via 128MB (1024Mb) Quad serial SPI Nor Flash
  • AS configuration for CvP support
  • Hard Processor System (HPS) Configuration Device
    • Serial NOR FLASH -SPI 128 Mbits connected to the HPS of the FPGA
    • One microSD 8 Go SDHC Class 10 (already insert into the support connector) with factory image boot

Communication & Interfaces

  • PCIe edge connector for Gen3 x4 (32Gb/s)
  • PCIe Root connector for Gen3 x4 (32Gb/s)
  • 2 x RJ45 copper connector 10/100/1000Base-T Ethernet (Through RGMII PHY) connected to the Fabric logic of the FPGA.
  • 1 x RJ45 copper connector 10/100/1000Base-T Ethernet (Through RGMII PHY) connected to the HPS of the FPGA.
  • One serial over USB High speed link (through USB Hub)
  • Mini USB connector B-type to enable the USB2.0 PHY OTG high speed, ULPI interface connected to the HPS of the FPGA.
  • FMC High Pin Count (HPC) compliant 1V8 interface
    • 160 LVCMOS (1.8V) usable as 80 LVDS (1.8V, 2.5V)
    • 4 dedicated LDVS clocks that respect the VITA57.1 pinout assignment usable as LVDS signals or 8 LVCMOS
    • 10 XCVR (up to: 14.2Gb/s)*

Memories

  • 4 x SDRAM DDR3 (a bandwidth of 8 bits per component for a total depth of 2GB) up to 2133 MT/s connected to the Fabric logic of the FPGA
  • 4 x SDRAM DDR3 (a bandwidth of 8 bits per component for a total depth of 2GB) up to 2133 MT/s connected to the HPS of the FPGA
  • Serial NOR FLASH -SPI 128 Mbits
  • 32Kb I2C EEPROM

Other resources

  • DisplayPort  Rev1.2 (up to 5.4Gbit/s)
  • MicroSD Card connector
  • MAX 10 Power supplies monitoring with its ADCs solution
  • +12V on a JACK/Edge PCIe connector
  • LCD Monitoring
  • DIP Switches
  • Diff Pair I/O (1 SMA pair)
  • On board UART over USB solution on Max 10 (µUSB connector).

Clock Circuitry

  • System clock 100 MHz (Max 10 / Arria® 10)
  • 3 SMA connectors (1 main input clock + 1 output programmable clock)
  • SILICON LABS tree innovative clock generation SI5341, on board PLL solution with very low Jitter which programmable 9 output clocks 100Hz to 800MHz LVDS to FPGA clock system
    • Input 0: Differential clock from PLL_CLKOUT FPGA output
    • Input 1: Single ended clock from SMA connector
    • Input 2: Dedicated default input clock for the SI341 from on board 100 MHz oscillator.

Board Size :

  • Length : 240 mm (9.45 inches)
  • Height :  111.15mm (4.38 inches) / Standard Height PCIe
  • Thickness : 1.57 mm (0.062 inches) / Standard Thickness PCIe

Power

  • 12V wall adapter or ATX / cables (US, UK, EU, JP)
  • Voltage and Current measurement capability of 2.5V, 1.5V, and 1.2V, 1.0V supplies (I²C path to FPGA)

* Production Device with transceiver speed grade 3 can reach 14.2 Gb/s chip to chip links, The VITA 57.1 standard allows interfaces up to 10 Gb/s

Deliverables

The Arria® 10 SoC FMC IDK includes hardware such as FMC Header, on-board USB Blaster, DDR4, PCIe capabilities and much more.

  • One Arria® 10 SoC FMC IDK board ( PCIe Bracket, Active fan already mounted)
  • Power desk adapter (AC/DC) 192W, 12V, 16A
  • Power cables (US, UK, EU, JP)
  • One USB standard cable A-type to Micro USB connector, 1.8 m length
  • One USB adapter USB A female / mini B male 20 cm length
  • One Ethernet cable CAT5E RJ-45, 17,7 cm length
  • One display port cable , 1.5 m length
  • Two SMA cables, 0.25 m length
  • One FMC loop back board
  • One PCIe loop back board
  • One LCD (2 lines x 16 characters, I2C, 5V)
  • ReFLEX innovative software interface (GUI on Windows) on USB Key with targeted test designs* and hardware documentation
  • OpenCL BSP HPC (Host-In-x86)
  • Starter Guide
  • 12-months limited warranty

Ordering informations

  • Development Kit (FPGA Arria® 10 SX 660) // RXCA10S066PF34-IDK00A
  • OpenCL BSP HPC (Host-In-x86) // RXCA10S0000F34-BSP00B (upon request)
  • OpenCL BSP HPC (Host-In-HPS) // RXCA10S0000F34-BSP00D (upon request)

* The USB key contains documentation (Starter Guide, Reference Manual, Schematics, Assembly files and Productbrief of the Kit) and test design of the board. When using the Arria® 10 SoC FMC IDK for the first time the user can launch the innovative Graphical User Interface and discover the Kit interfaces, applications and performances. The USB key also contains all the files required to enable and test FPGA and Software interfaces or help the user to start his own design. We provide the user an ALARIC Top_Arria10 folder which contains a blank Quartus II project intended for building a custom design "from scratch". It does not contain any HDL code except the port declaration of the top level. Pin assignments and timing constraints are provided for reference but should be reviewed and/or customized to fit design requirements.”

FAQ

Check our General FAQ for more common information.

This Development Kit respects the PCIe form factor with a standard height size. All the mechanical constraint rules are respected to allow the insertion of the Alaric board into a PCIe rack through its PCIe edge, by 4 connector and + 12 Volts PCIe connector supply.

This board offers a FMC front end interface to plug mezzanine card and access to 80 LVDS signals directly connected to the FPGA SX, usable as 160 LVCMOS single ended signal. On this interface you also have 10 Transceivers links up to 10 Gbps for each lane.

You can also connect your Alaric board to the network with a 10/100/1000 BaseT Ethernet interface with standard RJ45 connectors; two are directly connected through RGMMI PHY component to the HPS and one is connected on the fabric logic of the FPGA.

You can manage 8 internal clocks up to 800 MHz onboard with innovative programmable PLL drive by I²C bus connected to the CPLD MAX10 and the FPGA Arria® 10 SX.

This board is designed for prototyping PCIe host port by using the PCIe root Complex edge connector for Gen3 x4 (32Gb/s)

Finally, the Alaric board has a high end digital core based on Arria® 10 SX. It is connected to a 4GigaByte DDR3 component and offers two independent banks, one connected to the HPS of the FPGA.

->For more details about the Alaric PCIe FMC board and to get documentation, please email sales@reflexces.com or go on www.reflexces.com/contact

You must use Quartus programmer tools through USB blaster on board to reprogram the Development Kit, please check the latest Quartus version with your Intel FAE

Scenario 1:  You can program the FPGA Arria® 10 and (or) the MAX10 through USB blaster in JTAG mode.

Scenario 2: You can program the Arria® 10 with an image that is contained in Flash, in FPP 32 configuration mode.

Scenario 3:  At power-up, Arria® 10 automatically loads via a quad serial interface with its dedicated FLASH EPCQ, in AS configuration mode.

Scenario 4: “Configuration via Protocol”: One minimal configuration is contained in the EPCQ. This binary is loaded in the FPGA allowing to improve the PCIe access and permits to the software to load external image in the Arria® 10 (Configuration via Protocol (CvP))

Power supply monitoring:  the MAX 10 integrates Analog-to-digital converters (ADCs) to control power monitor system with the Intel modular ADC IP core implemented in it.

Serial communication: the MAX 10 integrates a serial logic bloc to enable an external communication (UART), the operator can take control through the USB front interface.

Programming system: You can program the Arria® 10 with an image that is contained in Flash. The MAX 10 integrates Parallel Flash Loader IP Core that allows to enable a FPP 32 configuration mode.

Configuration system: Partial reconfiguration IP Core has been instantiated. One minimal configuration can be uploaded into the Flash. This binary can be loaded in the FPGA during normal activity without any reboot and enables or redefines functions into the FPGA.

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