Attila Instant-DevKit Arria 10 GX FMC PCIe board

Product overview

The Arria 10 FPGA FMC Instant-Development Kit provides to developers the best Out-Of-The box experience combining the Best-In Class compact hardware platform and the most efficient intuitive software environment.

Its unique install and GUI interface allows an immediate start, and its reference designs enable fast turn-around designs shortening and securing the developments.

The target markets are as wide as Test & Measurement, Video capture and processing, High Performance Computing, Finance, Industrial and Medical.

Benefits & features

Designing for high performance serial transceiver applications using series 10 ALTERA FPGAs
Arria 10 GX 1150 KLEs.
Hardware, software design tools, IP, and pre-verified reference designs
Loopback boards, cables, and extension IOs board are available in the kit content
PCIe with 8 lanes at 8 Gb/s link rate (Gen3)
Advanced memory interface with DDR4 SODIMM Memory up to 16 GB, support ECC and Non ECC
Enabling serial connectivity with QSFP+ with 4 XCVR links: 12.5 Gb/s per link*
Develop networking applications with RJ45 copper connector 10/100/1000 Base-T Ethernet (Through RGMII PHY​)
Implement Video display applications with Display output port Rev 1.2 (up to 5.4Gbit/s)
Expand I/O connector with 2 connectors in order to improve a front end of 32 high speed link.
On board programmable PLL oscillator (Si5341), highly flexible and configurable clock generator/buffer.
The board respect the VITA57.1 standard, you can plug FPGA Mezzanine Card (FMC) on the front end
The FMC interface provides High Pin Count (HPC) fully populated, compliant +1.8V only (+vadj) :
  • 160 LVCMOS (1.8V) usable as 80 LVDS (1.8V, 2.5V)
  • 4 dedicated LDVS clocks that respect the VITA57.1 pinout assignment usable as LVDS signals or 8 LVCMOS
  • 10 XCVR (up to: 12.5 Gb/s)*

* Production Device with transceiver speed grade 4 can reach 12.5 Gb/s chip to chip links, The VITA 57.1 standard allows interfaces up to 10 Gb/s

Diagrams

Tech spec

Featured Device

  • FPGA Arria 10 GX 10AX115N4F40I3SG (1150K LEs in F40 package FBGA / production device)
  • ROHS compliant Arria10 FPGA PCIe FMC Instant-DevKit

Board programming

  • Onboard JTAG configuration circuitry to enable configuration over on board USB blaster
  • JTAG header provided to program the MAXV and access to the ARRIA 10.
  • Fast passive parallel (FPP) configuration via MAX®10 device and flash memory
  • Active Serial (AS) configuration via 128MB (1024Mb) Quad serial SPI Nor Flash
  • AS configuration for CvP support

Memories

  • DDR4 SODIMM interface (up to 16 GB, speeds up to 1200 MHz/2400 Mbps, 72 bits width support ECC and Non ECC)
  • 128MB (1024Mb) Quad SPI Nor Flash
  • 32Kb I2C EEPROM

Communication & Interfaces

  • 1 x RJ45 copper connector 10/100/1000Base-T Ethernet (Through RGMII PHY) connected to the FPGA.
  • 1 x QSFP+ optical cage (4 XCVR: 12.5 Gb/s per link)*
  • One serial over USB Bridge High speed link (through USB Hub) on front µUSB connector
  • 1 x PCIe edge connector for Gen3 x8 (32Gb/s)
  • FMC High Pin Count (HPC) compliant 1V8 interface
    • 160 LVCMOS (1.8V) usable as 80 LVDS (1.8V, 2.5V)
    • 4 dedicated LDVS clocks that respect the VITA57.1 pinout assignment usable as LVDS signals or 8 LVCMOS
    • 10 XCVR (up to: 12.5Gb/s)*
  • Extension connector SEARAY™ Series
    • 20 LVDS (1.8V) + 1 LVDS Clock
    • 22 XCVR (up to: 12.5 Gb/s)*

Note: Kit content FMC loopback board with TX/ RX display port connectors. Enables transceiver tuning and Signal Integrity verification.
Note: Kit content EXT loopback board with QSFP+ connector.

Clock Circuitry

  • System clock 100 MHz (Max 10 / Arria 10)
  • 3 SMA connectors (1 main input clock + 1 output programmable clock)
  • SILICON LABS tree innovative clock generation SI5341, on board PLL solution with very low Jitter which programmable 9 output clocks 100Hz to 800MHz LVDS to FPGA clock system
    • Input 0: Differential clock from PLL_CLKOUT FPGA output
    • Input 1: Single ended clock from SMA connector
    • Input 2: Dedicated default input clock for the SI341 from on board 100 MHz oscillator.

Other resources

  • DisplayPort Rev1.2 (up to 5.4Gbit/s)
  • MAX 10 Power supplies monitoring with its ADCs solution
  • LCD Monitoring
  • 5 x Push Button
  • 4 x DIP Switches
  • Diff Pair I/O (1 SMA pair)
  • On board UART over USB solution on Max 10 (µUSB connector).

Board Size

  • Length : 240 mm (9.45 inches)
  • Height : 111.15mm (4.38 inches) / Standard Height PCIe
  • Thickness : 1.57 mm (0.062 inches) / Standard Thickness PCIe

Power

  • 12V wall adapter or ATX / cables (US, UK, EU, JP)
  • 12V on a JACK/Edge PCIe connector
  • Voltage and Current measurement capability of 2.5V, 1.5V, and 1.2V, 1.0V supplies (I²C path to FPGA)

* Production Device with transceiver speed grade 4 can reach 12.5 Gb/s chip to chip links, The VITA 57.1 standard allows interfaces up to 10 Gb/s

Applications

Deliverables

The Arria 10 FPGA FMC IDK includes hardware such as FMC Header, on-board USB Blaster, DDR4, PCIe capabilities and much more.

  • One Arria 10 FPGA FMC IDK board ( PCIe Bracket, Active fan already mounted)
  • Power desk adapter (AC/DC) 192W, 12V, 16A
  • Power cables (US, UK, EU, JP)
  • One USB standard cable A-type to Micro USB connector, 1.8 m length
  • One Ethernet cable CAT5E RJ-45, 17,7 cm length
  • One display port cable , 1.5 m length
  • Two SMA cables, 0.25 m length
  • One 4GB sodimm module , x64 (Non ECC), single Rank, 2133 MT/s
  • One FMC loop back board
  • One Extension loop back board
  • One PCIe loop back board
  • One LCD (2 lines x 16 characters, I2C, 5V)
  • ReFLEX innovative software interface (GUI on Windows) on USB Key with targeted test designs* and hardware documentation
  • OpenCL BSP HPC
  • Starter Guide.
  • 12-months limited warranty
Ordering informations
Development Kit (FPGA Arria 10 GX 1150) // RXCA10X115PF40-IDK00A
OpenCL BSP HPC // RXCA10X0000F40-BSP00B
 
 *The USB key contains documentation (Starter Guide, Reference Manual, Schematics, Assembly files and Productbrief of the Kit) and test design of the board.
When using the ARRIA 10 FPGA FMC IDK for the first time the user can launch the innovative Graphical User Interface and discover the Kit interfaces, applications and performances.
 The USB key also contains all the files required to enable test interfaces or help the user to start his own design. We provide the user an ATTILA Top_Arria10 folder which contains a blank Quartus II project intended for building a custom design "from scratch". It does not contain any HDL code except the port declaration of the top level. Pin assignments and timing constraints are provided for reference but should be reviewed and/or customized to fit design requirements.”

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