The ALSE Aurora 64B/66B IP core is a very compact and optimized implementation of the Aurora 64B/66B protocol. Aurora 64B/66B is a lightweight and open protocol suitable for chip-to-chip, board-to-board and backplane applications using very high speed transceivers.
Compared to the 8B/10B version of the Aurora protocol, the 64B/66B flavor addresses the highest lanes speeds (when 8B/10B typically stops around 6 GBs per lane).
It also offers an effective bandwidth of up to 97%, instead of 80% for 8B/10B.
The IP therefore provides an efficient way to interconnect Intel and Xilinx FPGAs, or any other chip (ASIC, ASSP, etc …) using the Aurora 64B/66B protocol.
The Aurora 64B/66B IP core has been developed and tested for the REFLEX CES XpressGXS10-FH800G board.