in stock

Aurora 64B/66B IP Core

Product overview

The ALSE Aurora 64B/66B IP core is a very compact and optimized implementation of the Aurora 64B/66B protocol. Aurora 64B/66B is a lightweight and open protocol suitable for chip-to-chip, board-to-board and backplane applications using very high speed transceivers.

Compared to the 8B/10B version of the Aurora protocol, the 64B/66B flavor addresses the highest lanes speeds (when 8B/10B typically stops around 6 GBs per lane).
It also offers an effective bandwidth of up to 97%, instead of 80% for 8B/10B.

The IP therefore provides an efficient way to interconnect Intel and Xilinx FPGAs, or any other chip (ASIC, ASSP, etc …) using the Aurora 64B/66B protocol.

The Aurora 64B/66B IP core has been developed and tested for the REFLEX CES XpressGXS10-FH800G board.

Benefits & features

  • « In-System Probes and Sources » interface
  • Total of 16 lanes :
    • 4 independant instances (one per QSFP-DD)
    • 4 lanes per instance (QSFP28 compatible)
  • Data rate : @12.5Gbps / lane
  • PLLs configuration @312.5MHz
  • Shows framing mode with CRC
  • Full implementation of Aurora protocol
  • Full-duplex and Simplex Rx/Tx operations
  • 64-bits user datapath
  • Framing and Streaming interface
  • Up to 16 transceiver lanes per Aurora instance
  • User flow control
  • User K-block interface
  • Additional CRC for PDU frames
  • Native flow control
  • Clock compensation
  • and more





Keep me informed

If you want to know more about REFLEX CES, sign up for our newsletter to be updated on our initiatives, sectorial news and upcoming events.

Reflex CES Reflex CES