An SoC combines a hard processor system (HPS) – consisting of processors, peripherals, and memory controller – with the FPGA fabric, using a high-bandwidth interconnect backbone.
Typically, the REFLEX CES board based on Arria 10 SoC FPGA combines logic acceleration with Dual-core ARM Cortex-A9 MPCore processor unit.
Target markets includes automotive driver assistance, intelligent video surveillance, industrial automation, aerospace, defense, broadcast, and wireless communications. To learn more about these applications, please visit www.altera.com/socfpga and download the white paper.
Developers can quickly create their own custom ARM-based System on a Chip (SoC) to support unique system requirements, adapt to changing standards, accelerate algorithms critical time in hardware, scale a common hardware platform across a range of prices and performances points, and establish compelling product differentiation.
Intel's ARM-based SoCs helps reduce system power, system cost and board size, and increase system performances by integrating discrete FPGA, digital signal processing (DSP), and microprocessor devices into a single, user customizable ARM-based SoC.
No, the processor and FPGA can boot or configure in any order and in any sequence.
In addition to the HPS, Intel SoCs are available with additional multiport hard memory controllers (for use by logic in the FPGA fabric), serial transceivers, and hard PCI Express ports.
The Intel SoC FPGA Virtual Target is a PC-based fast functional simulation of an embedded development system for the Intel Cyclone V SoC and Arria V SoC FPGAs. Based on proven virtual prototyping technology from Synopsys, the Virtual Target represents a binary- and register-compatible, functional equivalent of the same dual-core ARM Cortex-A9 MPCore processors and CPU system peripherals featured in the SoC devices. The Virtual Target also lets you simulate board-level components such as DDR SDRAM, flash memory, and I/O devices. An optional FPGA-in-the-loop extension allows the PC-based simulation to interact with user-defined custom peripherals and hardware accelerators that can run on an Intel FPGA. Using the Virtual Target, you can start your project earlier, create device-specific production software, and later move it to your hardware platform with minimal effort.
The Virtual Target lets you do things that are complicated or impossible to do with real hardware, increasing your productivity and saving time. It puts more power debugging capabilities in the hands of the developers of complex, multicore systems, and will provide value to software developers long after silicon availability.
Intel's Qsys system integration tool saves you time and effort in the FPGA design process, simplifying the development of complex hardware systems by automatically generating an FPGA-optimized network-on-chip interconnect, system test bench, simulation model, software header file, and data sheet to expedite development across hardware and software teams. Qsys supports industry-standard interfaces, including ARM AMBA® AXITM, Avalon® Memory-Mapped, and Avalon Streaming interfaces.
Intel offers a broad portfolio of IP including embedded, interface protocol, video, image processing, DSP, and memory controller cores that can be integrated with user-designed IP to create a custom ARM processor systHow do the FPGA and HPS communicate?
The HPS shares the high-bandwidth interconnect backbone, capable of over 100-Gbps peak throughput, consisting of two 128-bit AMBA AXI bus bridges. IP built-in the FPGA fabric to have access to the HPS bus slaves via the FPGA-to-HPS bridge. Similarly, the HPS bus masters have access to bus slaves in the FPGA fabric via the HPS-to-FPGA bridge.
ARM is the most widely used 32-bit embedded processor today and is used in the broadest array of applications. In addition, ARM is supported by an extensive list of IP, tools, and silicon partners.
Yes, soft-core and hard-core processor technologies are complementary. The Nios® II processor will continue to offer tremendous value as a soft-core processor that can be used in any Intel FPGA. Because it is a soft processor, developers can add several Nios II processors to their systems to address a wide range of system requirements. Intel SoC developers can add one or more Nios II cores in the FPGA fabric for distributed control of FPGA functions.
FPGA Mezzanine Card, as defined in the VITA standard, provides a specification describing an I/O mezzanine module with connection to an FPGA carrier board. FPGA mezzanine modules, which plug to carrier board, offers a wide possibility of system interconnect as PCI, VME, VPX, CompactPCI, AdvancedTCA, MicroTCA, and many other.
A high-speed connector family SEAM/SEAF allows supporting up to 10 Gb/s transmission, supporting single ended and differential pairs.
The FMC mezzanine module can be used in high-pin count (HPC) or low-pin count(LPC), each one address reconfigurable I/O capability.
DP = differential pair
The gigabit interface signals are identified by the signals with a .‘DP.’ Prefix, and the associated reference clocks for use with the DP signals have a prefix of .‘GBTCLK.’.
DP[0..9]_M2C_P, DP[0..9]_M2C_N - These signals are arranged as differential pairs with signals having the .‘_P.’ postfix representing the positive component and signals with .‘_N.’ postfix representing the negative component.
DP[0..9]_C2M_P, DP[0..9]_C2M_N - These signals are arranged as differential pairs with signals having the .‘_P.’ postfix representing the positive component and signals with .‘_N.’ postfix representing the negative component.
The DP[0..9]_C2M differential pairs connect to the transmitters of the FPGA on the carrier card.
The DP[0..9]_M2C differential pairs connect to the receivers of the FPGA on the carrier card.
DP[0..31]_M2C_P, DP[0..31]_M2C_N, DP[0..31]_C2M_P, DP[0..31]_C2M_N - These signals form 32 multi-gigabit transceiver data pairs in cae of VITA57.4 for FMC+ standard
The LVDS defined pins are:
LA[00..33]_P, LA[00..33]_N - These signals are arranged as differential pairs with signals having the .‘_P.’ postfix representing the positive component and signals with .‘_N.’ postfix representing the negative component.
HA[00..23]_P, HA[00..23]_N - These signals are arranged as differential pairs with signals having the .‘_P.’ postfix representing the positive component and signals with .‘_N.’postfix representing the negative component.
HB[00..21]_P, HB[00..21]_N - These signals are arranged as differential pairs with signals having the .‘_P.’ postfix representing the positive component and signals with .‘_N.’ postfix representing the negative component.
-> More information on : VITA website
REFLEX CES has made the choice, since the appearance of the FMC standard, to develop several products able to meet the needs of clients and to answer a maximum of applications.
This will allow customers to target markets and specific applications in industries such as Datacom, Broadcast, Aerospace/Defense, Industrial and Instrumentation. Give to your designers the capabilities to enable work and accelerate their application development!
-> For more details about FMC pinout assignment overview and to get documentation, please email firstname.lastname@example.org or go on reflexces.com/contact
The USB key contains documentation (Starter Guide, Reference Manual, Schematics, Assembly files, product brief of the DevKit)
When using the Achilles Instant DevKit for the first time, the user can launch the innovative Graphical User Interface and discover the Kit interfaces, applications and performances.No need to install Quartus to access the board via JTAG communication! The board is delivered pre-programmed; you just need to plug-in the USB cable and launch the executable file of the GUI to start playing with the board in few seconds.
For the advanced users, we provide binary files such as jic, sof and pof files required to recover the delivery state. Test design folder, basically all the Quartus source code with the dedicated Intel test design example, are already compiled and ready to use on the Achilles module.
For Factory Re-set purposes binary files are provided (pof, jic).
The USB key also contains all the files required to enable interfaces to connect to the FPGA and help the user to start his own design. The test design example allows you to discover the features and capabilities of the board, through the complete Quartus project for each interface. You will find all the source files that you need (*.qpf, *.qsf, *. qsys, *.sdc, *.vhd….) to recompile this part or reuse it into your own HDL design code. We have integrated for each interface the IP core to enable the interface and performed an Intel test design (Pattern Generator and checker for the most part of the time).
We provide to the user a Top_Arria10 folder that contains a blank Quartus project intended for building a custom design "from scratch". It does not contain any HDL code except the port declaration of the top level. Pin assignments and timing constraints are provided for reference but should be reviewed and/or customized to fit design requirements.
Today we continue to deliver the PCIe boards with the Intel PSG-Ref Design and example.
We deliver with the board a complete Quartus project, included the PCI Express Avalon-MM High-Performance DMA Reference Design, with the Intel PSG PCIe IP core inside it.
You can install the PCIe driver and play with the windows framework made by Intel, make access to the FPGA memory through PCIe lane, in loopback mode. We have implemented and validated the Reference Design by realizing transfers data between the Arria 10 GX FPGA's internal memory and system memory.
This reference design includes a 64-bit Windows-based driver, 64-bit based software application that sets up the DMA transfers and manage the traffic.
The programming Clock Generator is a highly flexible and configurable clock generator/buffer. This component provides special and high-quality clock signals for high-speed transceivers. The clock generator Si5341 from Silicon Labs is controlled by the MAX10 through an I²C serial interface. The user can modify the frequency between 0.0001 MHz to 1.024 GHz
The clock transceivers corresponding to interface links are connected to three different transceivers banks, each featuring two reference clock inputs. At least one reference clock input per bank is fed by the same programmable PLL with a maximum skew of 100ps.
DDR memory controller reference clock input is also fed by the Si5341.
A test design, included in the board package, demonstrates the configuration of the SI5341. It uses a VHDL module which reads data from an internal RAM block and performs I²C accesses to configure the clock generator registers.
The RAM content is generated with a custom converter tool taking as input a ClockBuilder Pro project exported file. This allows performing any kind of configuration:
On main REFLEX CES’ boards you can manage 8 internal clocks up to 800 MHz onboard with this innovative programmable PLL drive by I²C bus connected to the CPLD and the FPGA. Most of the time the customer can select the input frequency that he needs for his dedicated application.
-> For more details about the Arria 10 FPGA Clock tree overview and to get documentation, please email email@example.com or go on reflexces.com/contact
Please open a request on the REFLEX CES support and give the serial board number (look at the white label with the number 100xxxxx)
Then, install Quartus DKE Edition version by downloading it on Intel PSG Software platform. You can find these at the Intel download center website hereafter : https://www.altera.com/downloads/download-center.html
Once they are installed, you may go to the Intel self-licensing website to generate the required license. Go to the Intel Support website and Sign in (Or create an account and then Sign in) : https://www.altera.com/mal-all/mal-signin.html
In the Self-Service Licensing Center, click on “Find it with your License Activation Code”
Then simply enter the license Activation Code « LAC » provided by REFLEX CES, and click on Activate Selected Products, if nothing appears please come back to REFLEX CES to claim another license.
A complete PCIe solution* is under development at REFLEX CES with Linux and Windows driver completed by custom API (Firmware and Software libraries) with complex DMA bridges EPCQ, PCIe, CvP, DDR, QDR. [*Please contact REFLEX CES to have more details on the advancement of this solution]