FAQ

Basic technical Questions

An SoC combines a hard processor system (HPS) – consisting of processors, peripherals, and memory controller – with the FPGA fabric, using a high-bandwidth interconnect backbone.

Typically, the REFLEX CES board based on Arria 10 SoC FPGA combines logic acceleration with Dual-core ARM Cortex-A9 MPCore processor unit.

Target markets includes automotive driver assistance, intelligent video surveillance, industrial automation, aerospace, defense, broadcast, and wireless communications. To learn more about these applications, please visit www.altera.com/socfpga and download the white paper.

Developers can quickly create their own custom ARM-based System on a Chip (SoC) to support unique system requirements, adapt to changing standards, accelerate algorithms critical time in hardware, scale a common hardware platform across a range of prices and performances points, and establish compelling product differentiation.

Intel's ARM-based SoCs helps reduce system power, system cost and board size, and increase system performances by integrating discrete FPGA, digital signal processing (DSP), and microprocessor devices into a single, user customizable ARM-based SoC.

No, the processor and FPGA can boot or configure in any order and in any sequence.

  • The processor can boot first then configure, reconfigure, or partially reconfigure the FPGA under program control
  • The FPGA can configure first then release the processor to boot through one of its flash memory interfaces, or through logic implemented in the FPGA fabric
  • The processor can boot and FPGA configure through independent interfaces as if they were two discrete devices

In addition to the HPS, Intel SoCs are available with additional multiport hard memory controllers (for use by logic in the FPGA fabric), serial transceivers, and hard PCI Express ports.

The Intel SoC FPGA Virtual Target is a PC-based fast functional simulation of an embedded development system for the Intel Cyclone V SoC and Arria V SoC FPGAs. Based on proven virtual prototyping technology from Synopsys, the Virtual Target represents a binary- and register-compatible, functional equivalent of the same dual-core ARM Cortex-A9 MPCore processors and CPU system peripherals featured in the SoC devices. The Virtual Target also lets you simulate board-level components such as DDR SDRAM, flash memory, and I/O devices. An optional FPGA-in-the-loop extension allows the PC-based simulation to interact with user-defined custom peripherals and hardware accelerators that can run on an Intel FPGA. Using the Virtual Target, you can start your project earlier, create device-specific production software, and later move it to your hardware platform with minimal effort.

The Virtual Target lets you do things that are complicated or impossible to do with real hardware, increasing your productivity and saving time. It puts more power debugging capabilities in the hands of the developers of complex, multicore systems, and will provide value to software developers long after silicon availability.

Some examples:

  • Enhanced run control of multicore systems (e.g. you can start and stop cores individually)
  • Synchronous stop of the whole system for a better look at the system states
  • Loading of Linux into the Virtual Target's memory instead of waiting for the processor to boot
  • Instantaneous flash memory and ROM content updates to save time
  • Virtually unlimited logging of system event and transactions

Intel's Qsys system integration tool saves you time and effort in the FPGA design process, simplifying the development of complex hardware systems by automatically generating an FPGA-optimized network-on-chip interconnect, system test bench, simulation model, software header file, and data sheet to expedite development across hardware and software teams. Qsys supports industry-standard interfaces, including ARM AMBA® AXITM, Avalon® Memory-Mapped, and Avalon Streaming interfaces.

Intel offers a broad portfolio of IP including embedded, interface protocol, video, image processing, DSP, and memory controller cores that can be integrated with user-designed IP to create a custom ARM processor systHow do the FPGA and HPS communicate?

The HPS shares the high-bandwidth interconnect backbone, capable of over 100-Gbps peak throughput, consisting of two 128-bit AMBA AXI bus bridges. IP built-in the FPGA fabric to have access to the HPS bus slaves via the FPGA-to-HPS bridge. Similarly, the HPS bus masters have access to bus slaves in the FPGA fabric via the HPS-to-FPGA bridge.

ARM is the most widely used 32-bit embedded processor today and is used in the broadest array of applications. In addition, ARM is supported by an extensive list of IP, tools, and silicon partners.

Yes, soft-core and hard-core processor technologies are complementary. The Nios® II processor will continue to offer tremendous value as a soft-core processor that can be used in any Intel FPGA. Because it is a soft processor, developers can add several Nios II processors to their systems to address a wide range of system requirements. Intel SoC developers can add one or more Nios II cores in the FPGA fabric for distributed control of FPGA functions.

General questions about REFLEX CES' Instant-Development Kits

FPGA Mezzanine Card, as defined in the VITA standard, provides a specification describing an I/O mezzanine module with connection to an FPGA carrier board. FPGA mezzanine modules, which plug to carrier board, offers a wide possibility of system interconnect as PCI, VME, VPX, CompactPCI, AdvancedTCA, MicroTCA, and many other.

A high-speed connector family SEAM/SEAF allows supporting up to 10 Gb/s transmission, supporting single ended and differential pairs.

The FMC mezzanine module can be used in high-pin count (HPC) or low-pin count(LPC), each one address reconfigurable I/O capability.

DP = differential pair

The gigabit interface signals are identified by the signals with a .‘DP.’ Prefix, and the associated reference clocks for use with the DP signals have a prefix of .‘GBTCLK.’.

DP[0..9]_M2C_P, DP[0..9]_M2C_N - These signals are arranged as differential pairs with signals having the .‘_P.’ postfix representing the positive component and signals with .‘_N.’ postfix representing the negative component.

DP[0..9]_C2M_P, DP[0..9]_C2M_N - These signals are arranged as differential pairs with signals having the .‘_P.’ postfix representing the positive component and signals with .‘_N.’ postfix representing the negative component.

The DP[0..9]_C2M differential pairs connect to the transmitters of the FPGA on the carrier card.

The DP[0..9]_M2C differential pairs connect to the receivers of the FPGA on the carrier card.

DP[0..31]_M2C_P, DP[0..31]_M2C_N, DP[0..31]_C2M_P, DP[0..31]_C2M_N - These signals form 32 multi-gigabit transceiver data pairs in cae of VITA57.4 for FMC+ standard

The LVDS defined pins are:

LA[00..33]_P, LA[00..33]_N - These signals are arranged as differential pairs with signals having the .‘_P.’ postfix representing the positive component and signals with .‘_N.’ postfix representing the negative component.

HA[00..23]_P, HA[00..23]_N - These signals are arranged as differential pairs with signals having the .‘_P.’ postfix representing the positive component and signals with .‘_N.’postfix representing the negative component.

HB[00..21]_P, HB[00..21]_N - These signals are arranged as differential pairs with signals having the .‘_P.’ postfix representing the positive component and signals with .‘_N.’ postfix representing the negative component.

-> More information on : VITA website

REFLEX CES has made the choice, since the appearance of the FMC standard, to develop several products able to meet the needs of clients and to answer a maximum of applications.

  • Attila (Arria 10 GX FMC PCIe board Instant-Development Kit) based on the biggest FPGA from Intel in Arria 10 GX, respects the PCIe form factor with a standard height size. There are two connectors with the same height on the top of the board that offers a massive and flexible IOs possibility on the front end with 100 Bidirectional LVDS signals and 32 transceivers links.
  • Alaric (Arria 10 SoC FMC PCIe board Instant-Development Kit) based on Arria 10 SoC, combines a dual-core ARM* Cortex*-A9 MPCore* Hard Processor System (HPS) with programmable logic technology that includes an important number of hardened floating-point DSP blocks.
  • Achilles (Arria 10 SoC SoM Instant-Development Kit), also based on Arria 10 SoC with a very similar architecture to Alaric, offers a solution like nowhere else: Memory performances, form factor and dual FMC capabilities.
  • Sargon (Stratix 10 FPGA FMC+ Instant-Development Kit) provides to developers the best Out-Of-The box experience, by combining the Best-In Class compact hardware platform with the most efficient intuitive software environment. Target markets include High Performance Computing and IP & ASIC Prototyping

This will allow customers to target markets and specific applications in industries such as Datacom, Broadcast, Aerospace/Defense, Industrial and Instrumentation. Give to your designers the capabilities to enable work and accelerate their application development!

-> For more details about FMC pinout assignment overview and to get documentation, please email sales@reflexces.com or go on reflexces.com/contact

The USB key contains documentation (Starter Guide, Reference Manual, Schematics, Assembly files, product brief of the DevKit)

When using the Achilles Instant DevKit for the first time, the user can launch the innovative Graphical User Interface and discover the Kit interfaces, applications and performances.No need to install Quartus to access the board via JTAG communication! The board is delivered pre-programmed; you just need to plug-in the USB cable and launch the executable file of the GUI to start playing with the board in few seconds.

For the advanced users, we provide binary files such as jic, sof and pof files required to recover the delivery state. Test design folder, basically all the Quartus source code with the dedicated Intel test design example, are already compiled and ready to use on the Achilles module.

For Factory Re-set purposes binary files are provided (pof, jic).

The USB key also contains all the files required to enable interfaces to connect to the FPGA and help the user to start his own design. The test design example allows you to discover the features and capabilities of the board, through the complete Quartus project for each interface. You will find all the source files that you need (*.qpf, *.qsf, *. qsys, *.sdc, *.vhd….) to recompile this part or reuse it into your own HDL design code. We have integrated for each interface the IP core to enable the interface and performed an Intel test design (Pattern Generator and checker for the most part of the time).

We provide to the user a Top_Arria10 folder that contains a blank Quartus project intended for building a custom design "from scratch". It does not contain any HDL code except the port declaration of the top level. Pin assignments and timing constraints are provided for reference but should be reviewed and/or customized to fit design requirements.

Today we continue to deliver the PCIe boards with the Intel PSG-Ref Design and example.

We deliver with the board a complete Quartus project, included the PCI Express Avalon-MM High-Performance DMA Reference Design, with the Intel PSG PCIe IP core inside it.

You can install the PCIe driver and play with the windows framework made by Intel, make access to the FPGA memory through PCIe lane, in loopback mode. We have implemented and validated the Reference Design by realizing transfers data between the Arria 10 GX FPGA's internal memory and system memory.

This reference design includes a 64-bit Windows-based driver, 64-bit based software application that sets up the DMA transfers and manage the traffic.

The programming Clock Generator is a highly flexible and configurable clock generator/buffer. This component provides special and high-quality clock signals for high-speed transceivers. The clock generator Si5341 from Silicon Labs is controlled by the MAX10 through an I²C serial interface. The user can modify the frequency between 0.0001 MHz to 1.024 GHz

The clock transceivers corresponding to interface links are connected to three different transceivers banks, each featuring two reference clock inputs. At least one reference clock input per bank is fed by the same programmable PLL with a maximum skew of 100ps.

DDR memory controller reference clock input is also fed by the Si5341.

A test design, included in the board package, demonstrates the configuration of the SI5341. It uses a VHDL module which reads data from an internal RAM block and performs I²C accesses to configure the clock generator registers.

The RAM content is generated with a custom converter tool taking as input a ClockBuilder Pro project exported file. This allows performing any kind of configuration:

  • Setting output clock frequencies
  • Switching from input clock source

On main REFLEX CES’ boards you can manage 8 internal clocks up to 800 MHz onboard with this innovative programmable PLL drive by I²C bus connected to the CPLD and the FPGA. Most of the time the customer can select the input frequency that he needs for his dedicated application.

-> For more details about the Arria 10 FPGA Clock tree overview and to get documentation, please email sales@reflexces.com or go on reflexces.com/contact

Please open a request on the REFLEX CES support and give the serial board number (look at the white label with the number 100xxxxx)

Then, install Quartus DKE Edition version by downloading it on Intel PSG Software platform. You can find these at the Intel download center website hereafter : https://www.altera.com/downloads/download-center.html

Once they are installed, you may go to the Intel self-licensing website to generate the required license. Go to the Intel Support website and Sign in (Or create an account and then Sign in) : https://www.altera.com/mal-all/mal-signin.html

In the Self-Service Licensing Center, click on “Find it with your License Activation Code”

Then simply enter the license Activation Code « LAC » provided by REFLEX CES, and click on Activate Selected Products, if nothing appears please come back to REFLEX CES to claim another license.

A complete PCIe solution* is under development at REFLEX CES with Linux and Windows driver completed by custom API (Firmware and Software libraries) with complex DMA bridges EPCQ, PCIe, CvP, DDR, QDR. [*Please contact REFLEX CES to have more details on the advancement of this solution]

 

Attila Instant-Development Kit

This Development Kit respects the PCIe form factor with a standard height size. All the mechanical constraint rules are respected to allow the insertion of the Attila board into a PCIe rack through its PCIe edge by 8 connector and + 12 Volts PCIe connector supply.

There are two connectors with the same height on the top of the board: FMC and Extension connector. These interfaces offers a massive and flexible IOs possibility on the front end with 100 Bidirectional LVDS signals and 32 transceivers link.

You can also connect your Attila board to the network with a bandwidth up to 40 Gigabits per second with the Optical connector QSFP+.

You can manage 8 internal clocks up to 800 MHz onboard with innovative programmable PLL drive by I²C bus connected to the CPLD MAX10 and the FPGA Arria 10 GX.

Finally, the ATTILA board has a high end digital core based on Arria 10 GX. It is connected to a 4GigaByte DDR4 SODIMM module.

-> For more details about the Attila PCIe FMC board and to get documentation, please email sales@reflexces.com or go on www.reflexces.com/contact

DDR4 SODIMM Models from 4GB to 16 GB, ECC or Non ECC from Micron:

MTA16ATF1G64HZ-2G1 : 8GB, x64 ( Non ECC), dual Rank, 2133 MT/s

MTA18ASF1G72HZ-2G1 : 8GB, x72 (ECC), dual Rank, 2133 MT/s

MTA16ATF2G64HZ-2G3 : 16GB, x64 ( Non ECC), dual Rank, 2400 MT/s

MTA18ASF2G72HZ-2G3 : 16GB, x72 (ECC ), dual Rank, 2400 MT/s

Development Kit content:
MTA8ATF51264HZ-2G1 : 4GB , x64 ( Non ECC), single Rank, 2133 MT/s

How to program my MAX 10 and Arria 10 on my Attila board?

You must use Quartus programmer tools through USB blaster on board to reprogram the Development kit, please check the latest Quartus version with your Intel FAE

Scenario 1:  You can program the FPGA Arria10 and/or the MAX10 through USB blaster in JTAG mode.

Scenario 2: You can program the Arria10 with an image that is contained in Flash, in FPP 32 configuration mode.

Scenario 3:  At power-up, Arria10 automatically loads via a quad serial interface with its dedicated FLASH EPCQ, in AS configuration mode.

Scenario 4: “Configuration via Protocol”: One minimal configuration is contained in the EPCQ. This binary is loaded in the FPGA, allowing to improve the PCIe access and permitting to the software to load external image in the Arria 10 (Configuration via Protocol CvP)

Alaric Instant-Development Kit

This Development Kit respects the PCIe form factor with a standard height size. All the mechanical constraint rules are respected to allow the insertion of the Alaric board into a PCIe rack through its PCIe edge, by 4 connector and + 12 Volts PCIe connector supply.

This board offers a FMC front end interface to plug mezzanine card and access to 80 LVDS signals directly connected to the FPGA SX, usable as 160 LVCMOS single ended signal. On this interface you also have 10 Transceivers links up to 10 Gbps for each lane.

You can also connect your Alaric board to the network with a 10/100/1000 BaseT Ethernet interface with standard RJ45 connectors; two are directly connected through RGMMI PHY component to the HPS and one is connected on the fabric logic of the FPGA.

You can manage 8 internal clocks up to 800 MHz onboard with innovative programmable PLL drive by I²C bus connected to the CPLD MAX10 and the FPGA Arria 10 SX.

This board is designed for prototyping PCIe host port by using the PCIe root Complex edge connector for Gen3 x4 (32Gb/s)

Finally, the Alaric board has a high end digital core based on Arria 10 SX. It is connected to a 4GigaByte DDR3 component and offers two independent banks, one connected to the HPS of the FPGA.

->For more details about the Alaric PCIe FMC board and to get documentation, please email sales@reflexces.com or go on www.reflexces.com/contact

You must use Quartus programmer tools through USB blaster on board to reprogram the Development Kit, please check the latest Quartus version with your Intel FAE

Scenario 1:  You can program the FPGA Arria10 and (or) the MAX10 through USB blaster in JTAG mode.

Scenario 2: You can program the Arria 10 with an image that is contained in Flash, in FPP 32 configuration mode.

Scenario 3:  At power-up, Arria 10 automatically loads via a quad serial interface with its dedicated FLASH EPCQ, in AS configuration mode.

Scenario 4: “Configuration via Protocol”: One minimal configuration is contained in the EPCQ. This binary is loaded in the FPGA allowing to improve the PCIe access and permits to the software to load external image in the Arria 10 (Configuration via Protocol (CvP))

Power supply monitoring:  the MAX 10 integrates Analog-to-digital converters (ADCs) to control power monitor system with the Intel modular ADC IP core implemented in it.

Serial communication: the MAX 10 integrates a serial logic bloc to enable an external communication (UART), the operator can take control through the USB front interface.

Programming system: You can program the Arria 10 with an image that is contained in Flash. The MAX 10 integrates Parallel Flash Loader IP Core that allows to enable a FPP 32 configuration mode.

Configuration system: Partial reconfiguration IP Core has been instantiated. One minimal configuration can be uploaded into the Flash. This binary can be loaded in the FPGA during normal activity without any reboot and enables or redefines functions into the FPGA.

Achilles Instant-Development Kit

The Achilles Instant-Development Kit, based on the A10 SoC SoM Turbo version, provides to developers the best Out-Of-The-Box experience, with all the parts that a customer can require to start the System-On-Module.

The Achilles DevKit is delivered with a starter board that provides all the interfaces to communicate with the FPGA and the HPS

-> For more details about the Achilles SoM module main features and to get documentation, please email sales@reflexces.com or go on www.reflexces.com/contact

The Achilles Instant-Development Kit includes the following elements:

  1. Arria 10 SoC SoM Turbo Version with its custom heat spreader and fan sink
  2. One Starter board to use the Arria 10 SoC SoM (find out more on the next question)
  3. One Power desk adapter (AC/DC), 12V, 108W
  4. Four Power cables (US, UK, EU, and JP)
  5. One USB standard cable A-type to Micro USB connector, 1.8 m length
  6. One USB standard female cable A-type to Mini USB connector B-type
  7. One USB standard cable A-type to Micro USB3.0, 1m length
  8. Two Ethernet CAT5E RJ-45 cables
  9. USB Key: REFLEX innovative software interface (GUI / Windows) with test designs and documentation
  10. Quartus DKE license (Development Kit Edition Software) One-year evaluation.

When you purchase an Achilles Development Kit, it will also include the Starter board. The starter board includes:

  • USB connectors to set up the SoM, JTAG, UART, RJ45 and serial interfaces.
  • Onboard USB Blaster JTAG configuration circuitry.
  • One µUSB connector allows interfacing UART HPS.
  • One connector for connecting a Linear DC1613A USB cable PMBus interface: Drive the digital Power System management on board.
  • 0, GPIF II interface fixed at 8 bits on the PHY USB3. Cypress CYUSB3013-BZXC
  • 2x 10/100/1000 MBits RJ 45 connector

The Arria 10 SoC SoM offers several versions that depends on the FPGA performances needs and the use of the board.

Lite version: provides the industry's lowest system cost and power, along with performance levels that makes the device family ideal for differentiating your high-volume applications.

Turbo version: provides high processing capabilities with the 600KLEs and DDR4 high performances levels that makes the device family ideal for complex applications. The dual FMC capabilities allows to interconnect this module very easily with the complete system.

Industrial version: provides industrial temperature product that allows you to use FPGAs and CPLDs, memories and complete design in high-temperature environments, such as automotive telematics, infotainment, and driver assistance systems, as well as temperature-sensitive military and industrial applications.

-> For more details about the module versions and to get documentation, please email sales@reflexces.com or go on www.reflexces.com/contact

The dual FMC capability is the latest idea of REFLEX CES and it takes shape through Achilles : The module can be plugged on a customer carrier board with the two FMC bottom connectors, and offers front panel IO possibilities with a mix of FMC modules plugged on the two FMC Top connectors

The Achilles System-On-Module can be used as FPGA Mezzanine Card & carrier board at the same time!

Do not forget that there are four FMC connectors, but the two mirror connectors (Top and Bottom on each side) share the same signals, the use of these two connectors is exclusive, one of the two connectors can be used one at a time.

Typically, the panel IO functionality was fixed in form factor cards, or it was configured with a fixed front panel IO module. Changing the front panel IO functionality means replacing the complete system. The FMC allows us to create dedicated processing bridge for a wide range of Input / Output data, video , audio, networking and many others signals processing without replacing the all system.

The dual FMC capabilities provides a flexible solution allowing multi configurable I/O front-end for FPGAs

A FMC SoM can provide a flexible solution for custom carrier boards and avoids a long and complicated time to design the digital heart of the system.

A SoM is a highly integrated System-on-Chip module that can be considered as computer-on-module technology coupled with FPGA flexibility for more complex projects.

If you design a baseboard on which the Achilles SoC module will be installed, you need to provide SEAF Female connectors (the module is equipped with SEAM on its bottom side)

To obtain a total stack Height of 10 mm between the carrier board and the module, you must use the following reference: SAMTEC P/N: ASP-134486-01 (SEAF-40-06.5-10-A)

To obtain a total stack Height of 7 mm between the carrier board and the module, you must use the following reference: SAMTEC P/N:  SEAF-40-05.0-10-A

-> If you want to have a different stack height, you must use the family SAMTEC SEARAY SEAM/SEAF connector; please refer and ask to the REFLEX CES support to know all the possible stack-height

If you design a Mezzanine board which is installed on Top of the Achilles SoC module, you need to provide SEAM Male connectors (the module is equipped with SEAF on its top side)

To obtain a total stack Height of 10 mm between the carrier board and the module, you must use the following reference: SAMTEC P/N: ASP-134488-01 (SEAM-40-06.5-10-A)

  • Power supply: +12V, +3.3V, +Vadj, Vref
  • 1 standard signals: Presence, Power Good GA, JTAG, I²C
  • Clock distribution with bidirectional and reference clocks: LVDS Clocks, Ref Clocks
  • 80 Differential Pairs in three LVDS groups
    • (usable 160 single ended)
    • HPC: LPC (LA [00:33]) + HA [00:23] + HB [00:21]
  • 10 High Speed SERDES, with two SERDES clocks, 10 Gbps
  • To avoid power failure, the +1.8V power supply is not provided on the Bottom connector

-> An Excel sheet with legends that describes what kind of signals are connected to the FPGA: LVDS, LVCMOS to standard Bank IOs FPGA, Transceivers to the XCVR bank FPGA, HPS is available upon request: Please contact the sales team to obtain more details on this topic at sales@reflexces.com or go on www.reflexces.com/contact

-> For more details about the FMC pinouts assignment and to get documentation, please email sales@reflexces.com or go on www.reflexces.com/contact

  • Presence, Power Good GA, JTAG, I²C
  • Clock distribution with bidirectional and reference clocks: LVDS Clocks, Ref Clocks
  • 80 Differential Pairs in three LVDS groups
    • (usable 160 single ended)
    • HPC: LPC (LA [00:33]) + HA [00:23] + HB [00:21]
  • 10 High Speed SERDES, with two SERDES clocks
  • No power supply providing or incoming from this connector

-> An Excel sheet with legends that describes what kind of signals are connected to the FPGA: LVDS, LVCMOS to standard Bank IOs FPGA, Transceivers to the XCVR bank FPGA, HPS is available upon request : Please contact the sales team to obtain more details on this topic at sales@reflexces.com or go on www.reflexces.com/contact

-> For more details about the FMC pinouts assignment and to get documentation, please email sales@reflexces.com or go on www.reflexces.com/contact

  • 1 standard signals: +12V, +3.3V, +Vadj, Vref Presence, Power Good GA, JTAG, I²C
  • Clock distribution with bidirectional and reference clocks: LVDS Clocks, Ref Clocks
  • 33 Differential Pairs in one LVDS group
    • (33 pairs +2 single ended)
    • (usable 68 single ended)
    • HPC: LPC (LA [00:33])
  • 10 High Speed SERDES, with Two SERDES clocks
  • No HPS interface

 

-> An Excel sheet with legends that describe what kind of signals is connected to the FPGA: LVDS, LVCMOS to standard Bank IOs FPGA, Transceivers to the XCVR bank FPGA, HPS is available upon request. Please contact the sales team to obtain more details on this topic.

-> For more details about the FMC pinouts assignment and to get documentation, please email sales@reflexces.com or go on www.reflexces.com/contact

  • Power supply Input: +12V
  • 1 standard signals: Presence, Power Good GA, JTAG, I²C
  • Clock distribution with bidirectional and reference clocks: LVDS Clocks, Ref Clocks
  • 33 Differential Pairs in one LVDS group
    • (33 pairs +2 single ended)
    • (usable 68 single ended)
    • HPC: LPC (LA [00:33])
  • 14 High Speed SERDES, with Two SERDES clocks
  • Full HPS interface accessible by this connector
  • SoM A10 Power supply input from this connector

-> An Excel sheet with legends that describe what kind of signals is connected to the FPGA: LVDS, LVCMOS to standard Bank IOs FPGA, Transceivers to the XCVR bank FPGA, HPS is available upon request. Please contact the sales team to obtain more details on this topic.

-> For more details about the FMC pinouts assignment and to get documentation, please email sales@reflexces.com or go on www.reflexces.com/contact

You need to use the SEARAY™ High-Speed High-Density Array Cable Assembly from Samtec. Please refer to the SAMTEC web page HDR Cable Assembly Options for FMC to know all the interconnect possibilities.

This PCIe Carrier Board is an optional extra product for clients looking for a PCIe format board.

 

REFLEX CES Arria 10 SoC module can be plugged on this PCIe Carrier Board. The PCIe carrier board then provides access to all of the features of the System-On-Module:

  • USB connectors to set up the SoM, JTAG, UART, RJ45 and serial interfaces.
  • Onboard USB Blaster JTAG configuration circuitry.
  • One µUSB connector allows interfacing UART HPS.
  • One connector for connecting a Linear DC1613A USB cable PMBus interface: Drive the digital Power System management on board.
  • 0, GPIF II interface fixed at 8 bits on the PHY USB3. Cypress CYUSB3013-BZXC
  • 2x 10/100/1000 MBit RJ 45 connector

It also provides access to further functions, including:

  • QSFP+: Quad Small Form-factor Pluggable up to 4 lanes at 10.3125 Gbps
  • SFP+: Small Form-factor Pluggable with 1 lane at 10.3125 Gbps
  • PCIe x8 Gen3: Hard IP PCIe implemented and rooting to enable lanes at 8 Gbps
  • Wifi solution with the Atmel IEEE 802.11 b/g/n Link Controller SoC

 

The PCIe carrier board is delivered with schematics and VHDL test designs

 

-> For more details about the Achilles Instant DevKit and to get documentation, please email sales@reflexces.com or go on www.reflexces.com/contact

You will have two independent memory banks with four chips with density 8Gb or 16Gb each bank : each memory bank of the Arria 10 SoC SoM address a 32 bits data bus width by using two chip x16bits, with a clock rate at 1200MHz or 2666MHz (according to the module version)

A test design that validates the DDR4 memory connected to the FPGA is available, it uses the Intel example design generated with the DDR4 controller IP.

The final user can use the memory bank connected physically to the HPS without using the HPS to add this memory interface to the FPGA. The DDR4 interface of the HPS uses the Bank IO, shared with the FPGA, and that can be used by the FPGA only. If the HPS is alive, the DDR4 is normally used to execute the Operating system pattern and cannot be used as additional memory interface to the FPGA.

Already mounted, the thermal solution is composed of two parts: Heat spreader and Heat sink, that offers air-cooled and conduction-cooled solutions depending of the customer environment.

If you want to use the SoM A10 in standalone application, on a desk or ambient environment without mechanical constraint, you can leave the FAN top of the set and ensure a good cooling solution.

If you want to integrate the SoM A10 into an enclosure, a server, or a custom rack, you need to evaluate the operating range temperature with requirements in terms of airflow. The heatsink can be upgraded by customization, to offer better airflow evacuation.

For highly constrained industrial environments, please refer to industrial version of the SoM, called “industrial”

This document provides information for designing a custom Carrier Board for the Arria10 SoC SoM Module. It includes reference schematics for the external circuitry, required to implement the different interfaces available on the module.

This design guide is intended for electronics engineers designing a carrier board for the Arria10 SoC SoM.  In most cases, the examples come from designs that have been built and tested.

 

The CDG gives a list of suggestions for designing with high-speed differential signals and single ended signals:

  • Use controlled impedance PCB traces.
  • Keep the trace lengths.
  • Trace-length constraints, separation, group matched
  • Clocks/periodic signals (CMOS/TTL) recommendations
  • Route differential signals and PCB layers, Routing Considerations

The PHY component is connected to the Core Fabric of the Arria 10 SX, the GPIF II interface is fixed at 8 bits on the PHY. This enables interface frequencies up to 100 MHz so a maximum work data rate of 800 Mb/s data rates after encoding, corresponding to High-Speed mode.

In case of redesign or creation of a similar interface by using the FMC interfaces, we advise to use the complete data bus of the FX3 by using the 32 bits to provide SuperSpeed solution with a symbol rate up to 5 Gbit/s for an effective data rate at 4 Gbit/s (500 MB/s).

When using the module alone without using our Starter board, you can supply the SoM A10 with an input voltage in the range of +5.5V-17V.

The components at the top in the power supply tree can absorb an input up to +17V. But, in this case, you will not be able to connect FMC modules to the TOP connectors of the module because VITA57.1 imposes a maximum of + 12V +/- 5%. In addition, to offer the input voltage for the internal power tree, we connect the + Vin directly to the pins of the FMC connectors. So be careful when designing your own power supply input and limitation.

When using a starter board or PCIe carrier board designed by REFLEX CES, you will see that we have a protective, surge and reverse mounting. You will be able to supply an input voltage in the range of + 9.5V-13.45V

Concerning the Arria 10 SX SoM, we use power supply unit with a CUI INC AC adapter:

P/N: SDI120-12-U

Input: 100-240V ≈ 47-63Hz 2.8A Max

Output (DC): 12V / 9 A => 108W

LTM4675 Power rail:

First stage of the Power supply tree, the DC/DC converter has ADC inside that allows it to measure the output voltage and has also PMBus driver to communicate on the PMbus. We can monitor the power supply input +12V and the output voltage from this component which provide the primary power rail +5V.

-> For more details about the power supply of the Achilles SoM module and to get documentation, please email sales@reflexces.com or go on www.reflexces.com/contact

The Power Management Bus (PMBus) is a standard power-management protocol. This flexible and highly versatile standard allows communications between devices, based on both analog and digital technologies. It is a standard way to communicate with power Converters and FPGA over a Digital communications Bus. It is similar to the I²C protocol.

 

Below, you will find the list of the channels which are monitored and managed by the CPLD MAX 10 or external operator with the DC1613A through PMBus connector (available on the Starter board or the PCIe carrier board):

 

LTC2980 Power supervisor device A :

channels 0: 3V3 U

channels 1: 3V3 I (Rshunt = 10 mohms)

channels 2: 2V5 U

channels 3: 2V5 I (Rshunt = 510 mohms)

channels 4: VTT_DDR4 U (0.6V)

channels 5: no current on this channel

channels 6: VDDQ U

channels 7: VDDQ I (Rshunt = 100 mohms)

 

LTC2980 Power supervisor device B :

Channels 0: 0V9 U

Channels 1: 0V9 I (Rshunt = 5 mohms)

Channels 2: 0V95 U

Channels 3: 0V95 I (Rshunt = 10 mohms)

Channels 4: 1V2 U

Channels 5: 1V2 I (Rshunt = 30 mohms)

Channels 6: 1V8 U

Channels 7: 1V8 I (Rshunt = 10 mohms)

 

LTM4675 Power rail :

First stage of the Power supply tree, the DC/DC converter has ADC inside that allows it to measure the output voltage and has also PMBus driver to communicate on the PMbus. We can monitor the power supply input +12V and the output voltage from this component which provide the primary power rail +5V.

MAX® 10 FPGAs allows non-volatile integration, with NOR flash technology inside the device. Unlike CPLDs, MAX 10 FPGAs also includes full-featured FPGA capabilities, such as Nios® II soft core embedded processor support, digital signal processing (DSP) blocks.

With the Arria 10 SoC SoM, the Max10 CPLD is used as an on-board system control which manage the voltage, temperature, power good, JTAG and communicate with the FPGA and the extremal world through UART and I²C link.

-> For more details about the power supply of the Achilles SoM module and to get documentation, please email sales@reflexces.com or go on www.reflexces.com/contact

In the Arria 10 SoC, several boot configurations are possible:

  • The HPS boot and FPGA configuration occurs separately (Achilles devkit configuration)
  • The HPS boots first and configures the FPGA
  • The HPS boots from the FPGA after the FPGA is configured

 

Scenario 1 :  You can program the Arria 10 FPGA and (or) the MAX 10 through USB blaster in JTAG mode.

Scenario 2 :  At power-up, Arria 10 FPGA automatically loads via a quad serial interface with its dedicated FLASH EPCQ, in AS configuration mode.

Scenario 3 :  After having initialized the HPS, the BootROM determines the device where the bootloader is stored using the BSEL pins ( NAND, QSPI, µSD…the FPGA IOs can be used)

Scenario 4 :  After having initialized and ready to use the HPS, can load a bitstream from external , as GbE and program the FPGA

Scenario 5  :  “Configuration via Protocol” : One minimal configuration is contained in the EPCQ. This binary is loaded in the FPGA allowing the improvement of the PCIe access and permits the software to load external image in the Arria 10

-> For more details about the programming of the Achilles SoM module and to get documentation, please email sales@reflexces.com or go on www.reflexces.com/contact

The programming Clock Generator is a highly flexible and configurable clock generator/buffer. This component provides special and high-quality clock signals for high-speed transceivers. The clock generator Si5341 Rev D from Silicon Labs is controlled by the MAX10 through an I²C serial interface. The user can modify the frequency between 0.0001 MHz to 1.024 GHz

The clock transceivers corresponding to interface links are connected to three different transceivers banks, each featuring two reference clock inputs. At least one reference clock input per bank is fed by the same programmable PLL with a maximum skew of 100ps.

DDR4 controller reference clock input is also fed by the Si5341.

A test design, included in the board package, demonstrates the configuration of the SI5341. It uses a VHDL module which reads data from an internal RAM block and performs I²C accesses to configure the clock generator registers.

 

The RAM content is generated with a custom converter tool taking as input a ClockBuilder Pro project exported file. This allows performing any kind of configuration:

  • Setting output clock frequencies
  • Switching from input clock source

 

-> For more details about the clock circuitry of the Achilles SoM module and to get documentation, please email sales@reflexces.com or go on www.reflexces.com/contact

Intel 's Qsys system integration tool saves you time and effort in the FPGA design process, simplifying the development of complex hardware systems by automatically generating an FPGA-optimized network-on-chip interconnect, system Testbench, simulation model, software header file, and data sheet to expedite development across hardware and software teams. Qsys supports industry-standard interfaces, including ARM AMBA® AXITM, Avalon® Memory-Mapped, and Avalon Streaming interfaces.

Intel offers a broad portfolio of IP including embedded, interface protocol, video, image processing, DSP, and memory controller cores that can be integrated with user-designed IP to create a custom ARM processor system.

The HPS shares the high-bandwidth interconnect backbone, capable of over 100-Gbps peak throughput, consisting of two 128-bit AMBA AXI bus bridges. IP built in the FPGA fabric have access to HPS bus slaves via the FPGA-to-HPS bridge. Similarly, HPS bus masters have access to bus slaves in the FPGA fabric via the HPS-to-FPGA bridge.

To build and debug HPS software, the suite of Intel design tools, Intel SoC Embedded Design Suite (SoC EDS), needs to be installed. The version to use is the Intel SoC EDS v16.1.0.196.

We provide all parts that the user needs to build his own software architecture:

  • The processor executes the 128 KB BootROM code which resides inside on-chip ROM. The main role of the BootROM is to initialize all required hardware components to boot up the next stage boot software, the U-Boot bootloader.
  • The bootloader used in the devkit is U-Boot, an open source bootloader used in many embedded devices.
  • The Operating System running on the HPS is Linux. So, the boot image loaded by U-boot is the kernel image. It is responsible for supporting all the hardware of the Achilles devkit handled by the HPS. The version used is a customized 4.1.22.
  • We provide two different root file systems to be mounted by the Linux kernel on the HPS:
    • One is based on the Linaro-nano release based on Ubuntu 15.04. It has been customized to add SSH support, network setup and HPS test scripts and programs.
    • The second one is built with Buildroot and based on Busybox.

The size of the SoM is 86mm x 95 mm

The figures into the Carrier design Guide documentation shows the Arria 10 SoC SoM form factor with connector and attachement holes position, views from the TOP side of the board, dimensions in millimeters. Detailled STEP File of the Arria10 SoC SoM is available upon request, please contact support or your sale representative for more information.

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