Featuring an ARM dual-core Cortex-A9 MPCore and up to 660KLEs of advanced low-power FPGA logic elements, the Arria® 10 SoC combines the flexibility and ease of programming of a CPU with the configurability and parallel processing power of an FPGA.
The target markets are as wide as Automotive, Video Broadcast, Machine and Intelligent Vision, Industrial, Military, Test & Measurement and Medical.
This System On Module is also available in a Development Kit : The Achilles DevKit.
We also offer a PCIe Carrier Board as an optional extra product compatible with any of REFLEX CES Arria® 10 SoC SOM's, or can propose the design of a custom Carrier Board.
Please contact us directly if none are available on mouser.com
| Features | Description | Achilles "Turbo" | Achilles "Indus" | Achilles "Lite" |
| FPGA SoC | Arria® 10 FPGA with dual ARM® Cortex TM A9 MPCore TM processor based hard processor system (HPS), F34 package (1152 pins) | 10AS066H2F34I1HG Commercial Temp, speed grade -1 |
10AS066H2F34I1HG Industrial Temp, speed grade -1 |
10AS027H3F34E2SG Commercial Temp speed grade -2 |
| DDR4 Memory | 32bit wide bank for FPGA | 4GByte @2400MT/s | 2GByte @2400MT/s | |
| 32bit wide bank for HPS | 4GByte @2400MT/s | 2GByte @2133MT/s | ||
| Communication & Networking | 2 Gigabit Ethernet RGMII on the HPS | |||
| USB 3.0 using Cypress FX3 super speed controller |
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| USB 2.0 host/device OTG support connected to the HPS | ||||
| I²C link support connected to the HPS,EEPROM, Sensor Temp | ||||
| UART connected to System controller and to HPS | ||||
| FMC Connectors | Top Left High Pint Count (HPC) |
80 LVDS pairs (1.25Gbps) usable as 160 single ended LVCMOS1.8V 10 Serial transceivers channel (RX and TX) @7Gbps Power Suplies Output: +12/+3.3V/1.8V/ +VADJ = +1.8V |
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| Top Right Low Pin Count (LPC) |
33 LVDS pairs (1.25Gbps) usable as 66 single ended LVCMOS1.8V 10 Serial transceivers channel (RX and TX) @7Gbps Power Suplies Output: +12/+3.3V/1.8V/ +VADJ = +1.8V |
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| Bottom Left Low Pin Count (LPC) |
80 LVDS pairs (1.25Gbps) usable as 160 single ended LVCMOS 1.8V 10 Serial transceivers channel (RX and TX) @10Gbps No Power supply, respect +VADJ electrical standard (+1.8V) |
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| Bottom Right High Pint Count (HPC) |
33 LVDS pairs (1.25Gbps) usable as 66 single ended LVCMOS 1.8V 14 Serial transceivers channel (RX and TX) @10Gbps Power Suply +12 Hard Processing ARM peripheral I/Os (GbE,USB2.0,I²C,UART) FPGA peripheral I/Os (GPIF II= USB3.0) |
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| FPGA Configuration | Onboard JTAG configuration circuitry to enable configuration over USB | |||
| 512Mb Quad SPI Flash for remote upgrade and failsafe configuration | ||||
| Software Configuration | Nand Flash eMMC (Store operating Linux system :
U boot, Kernel and RootFS) |
32 GByte | 32GByte | 8GByte |
| Module dimensions | 86mm x 95mm (3.4 x 3.8 inches) | |||
| Weight | Turbo/indus module without Mechanics: 87.8g Lite module without Mechanics: 78.8g Heat Spreader: 93.9g | Heat Sink: 86.9g | Fan: 15.7g |
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| Temperature range | Commercial | Industrial | Commercial | |
| Ordering information | RXCA10S066PF34-SOM00T | RXCA10S066PF34-SOM00I | RXCA10S027PF34-SOM00L | |
Arria® 10 SoC disruptive System-on-Module by REFLEX CES :
Achilles Workshop by REFLEX CES :
Object detection demo using FPGA DNN IP :
Below are the videos regarding The Achilles DevKit :
Setting up your REFLEX CES Achilles Development Kit :
Exploration of REFLEX CES' Graphical User Interface (GUI) for the Achilles Development Kit :
Deliverables
Ordering Information
